MICHAEL BANE
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FPGAs for Energy Efficient Performant Computing

Field Programmable Gate Array (FPGA) technology promises high performance computing on a low power platform. Yet, despite their capabilities to deliver bespoke solutions that are faster and require less instantaneous power than either CPU or GPU technology, as well as recent interest shown by Intel acquiring Altera and AMD acquiring Xilinx, and being reconfigurable at run-time, FPGA are yet to be seen in the Top500 listings (of supercomputing facilities). The learning curve to obtain near-peak performance from the available logic takes longer than compared to getting near-peak performance from the general purpose CPU technologies with their mature compilers & toolchains. This is likely due to the emphasis on dataflow for FPGA compared to imperative (control flow) programming for CPUs and GPUs.

My previous research during the H2020 "Vineyard" project showed speed-up over CPU for neurosciences, and more recent research work via my Liverpool MSc student projects, has successfully led to implementations on a single Xilinx Alveo FPGA card that exceed performance (for given accuracy) in accelerating linear algebra (Hsieh) and financial (Carter) modelling. Supported by Xilinx and Dell, with Co-Investigators from Liverpool, Manchester & STFC Scientific Computing Division, I led a grant proposal to Excalibur "Hardware and Enabling Software (H&ES) Programme" worth total of £160K, which got to the final panel.

My current research includes (i) showing role of FPGA for effective compute, (ii) quantifying the savings in energy-to-solution as a result of using FPGA for effective compute. The main thrust of (i) in terms of efficiently automating near-peak efficiency use of FPGA for core scientific kernels will leverage the ideas from the Excalibur H&ES proposal. Namely, we shall select key computation kernels (such as the modern equivalent of [Colella, 2004]'s now famous "Seven Dwarfs" (aka "killer kernels")) and work closely with FPGA community/vendors to efficiently implement these to FPGA technology (or rule as inappropriate to be worth porting). Lessons from this will lead to an expert guide/workflow to support others in (designing &) porting algorithms to FPGA, flattening the learning curve and leading to more rapid take-up by the HPC community. We can then determine savings by comparative runs of real world applications on various computing platforms to quantify the savings achieved by use of FPGA technologies. Both Xilinx (leading FPGA vendor worldwide) and Microsoft (who expose FPGAs within their Azure cloud) have expressed interest in supporting this applied research.

My interests include:

I am PI of the UKRI netZero £120K project "Energy-aware heterogeneous computing at scale" (aka "Energetic"). This project, led by MMU with UCL, EPCC/University of Edinburgh & Newcastle as partners, runs until Dec2022 aims to test whether the use of heterogeneous architecture (use of FPGAs and GPUs alongside CPUs) could significantly reduce energy to solution and thus the energy consumed by UKRI data centres.

References

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